1. Field of the Invention
The present invention is generally in the field of electronics. More particularly, the present invention is in the field of electrical circuit design.
2. Background
A buffer circuit can be configured to receive a time varying input signal, such as a clock signal, and to output a corresponding time varying output signal with a greater load driving capability. For example, such buffer circuits can be critical in systems where a clock signal must be distributed to large loads.
In one type of conventional buffer circuit, inductors are used to “tune” the buffer circuit. The tuning is performed by estimating the total capacitive load to be driven by the buffer circuit and using appropriate buffer inductance values to achieve a desired resonance frequency, coinciding with the clock signal frequency. Since the buffer circuit provides high impedance when operating at the resonance frequency, it can provide a more stable output capable of driving large loads. Moreover, the high impedance reduces the buffer's power consumption.
However, parasitics, such as parasitic inductances, which exist in the interconnecting conductors between the buffer circuit and the capacitive load can cause the operation frequency of the buffer circuit to shift away from the desired resonance frequency. In addition, there may be interconnect resistances (e.g., metal resistance) between the buffer circuit and the loads, which can result in increased power consumption. Thus, the proper design and operation of the conventional buffer circuit typically requires highly accurate models (i.e., highly accurate approximations) of the parasitics in the interconnecting conductors. However, such accurate models of the parasitics can be both difficult and time consuming to determine and implement.
Thus, there is a need in the art for an inductor-tuned buffer circuit that allows for an improved modeling and design of the buffer circuit.